1. Field of the Invention
The present invention relates to a semiconductor circuit, and particularly to a test mode input detection circuit for a semiconductor device.
2. Description of the Related Art
For starting a special mode, for example a test mode or the like, semiconductor devices such as semiconductor memory devices employ a circuit to be activated only with a voltage that is higher than a normal input voltage.
FIG. 1 shows an example of a conventional test mode input detection circuit, wherein N-channel enhancement MOS transistors Tl to Tn have a short-circuited gate and drain and an n-channel depletion MOS transistor T11 has a short-circuited gate and source. These n+1 transistors are connected in series between an input terminal 10 of a usual circuit 20 and a ground.
Further an n-channel depletion MOS transistor T12 and an n-channel enhancement MOS transistor T13 are connected in series between a power source Vcc and the ground, to form an inverter. The gate of the transistor T13 is connected to a node Nl between the transistors Tn and T11, the gate of the transistor T12 is connected to the source thereof, and the source of the transistor T12 forms an output terminal SIG.
The input terminal 10 serves a usual circuit 20 (not used in a test) of a semiconductor device. Namely, when a voltage VIN applied to the input terminal 10 is lower than a normal voltage, i.e., the power source voltage Vcc, the usual circuit 20 is activated and the test circuit is not activated. The test circuit is activated, when the voltage VIN applied to the input terminal 10 exceeds the normal voltage.
When each of the transistors Tl to Tn has a threshold voltage of Vth, a collective threshold voltage of the n series-connected transistors Tl to Tn is nVth. Namely, these transistors will not be turned ON unless a voltage higher than nVth is applied there to. When nVth&gt;Vcc is established and when a normal voltage lower than the power source voltage Vcc is applied to the input terminal 10, the transistors Tl to Tn are turned OFF, the node Nl becomes low (L) level (ground level), and the output SIG becomes high (H) level, thereby establishing a non-test mode. If a semiconductor device connected to the test mode input detection circuit is a memory device, the non-test mode corresponds to a read/write mode.
When a high voltage (test voltage) VT higher than the power source voltage Vcc is applied to the input terminal 10, the transistors Tl to Tn are turned ON, and the node Nl provides a potential of VT minus nVth to the transistor T13. As a result, the transistor T13 is turned ON, and the output SIG is made L level for setting the test mode.
In this prior art, the test voltage VT applied to the input terminal 10 is, for example, 10 V, which is higher than the power source voltage Vcc of, for example, 5 V, for the normal operation. When the collective threshold voltage nVth fluctuates, the node voltage "VT minus nVth" is changed. If this node voltage is too low, the transistor T13 will not be turned ON, and the output SIG will not become L level, and as a result, the test mode will not be established.
If the collective threshold voltage nVth is too low, the transistors Tl to Tn may be turned on every by the power source voltage Vcc (which may also fluctuates) applied to the input terminal 10 for the normal mode, and accordingly, a current path will be formed from the input terminal 10 to the ground, to cause a leak current.